Search results for "network on chip"

showing 2 items of 2 documents

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…

010302 applied physicsStatic routingDynamic Source Routingnetwork on chip; routing; manufacturing faultComputer sciencebusiness.industryRouting tableDistributed computingPolicy-based routing02 engineering and technology01 natural sciences020202 computer hardware & architecturenetwork on chipRouting domainLink-state routing protocolrouting0103 physical sciencesMultipath routing0202 electrical engineering electronic engineering information engineeringmanufacturing faultbusinessHierarchical routingComputer network
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Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal

2014

International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Fe…

RTL modelingComputer scienceOrthogonal frequency-division multiplexing[SPI] Engineering Sciences [physics]Common Operators02 engineering and technologyGeneric hardware architecturesFFT- SDF[SPI]Engineering Sciences [physics]Gate arrayVHDL[ SPI ] Engineering Sciences [physics]0202 electrical engineering electronic engineering information engineeringGeneric hardware architectures Rake receiver FFT- SDF Common Operators 3D-Network on chip RTL modelingField-programmable gate arraycomputer.programming_languageVirtexbusiness.industry020208 electrical & electronic engineering020206 networking & telecommunicationsDigital architectureRake receiverComputer architectureEmbedded systemRake receiver3D-Network on chipbusinessCommunications protocolcomputer
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